1. Field of the Invention
The present invention relates to a programmable controller configured to execute a plurality of independent sequence programs in parallel.
2. Description of the Related Art
In general, in a programmable controller configured to perform sequence control, an execution of sequence programs, that is, an arithmetic and logical operation processing, is performed by a micro-processing unit (MPU) or application-specific integrated circuit (ASIC). The MPU or ASIC is alternatively used for the processing depending on instructions that constitute the sequence programs. The MPU is based on a single LSI that combines functions of a CPU, while the ASIC is an integrated circuit customized for a particular use.
Japanese Patent Application Laid-Open No. 2009-116445 discloses the following techniques (A) and (B) in which a plurality of independent sequence programs are executed by such a single programmable controller.
(A) Hardware comprising a single MPU 10, a single memory 20, and a single ASIC 30, as shown in FIG. 1. N number of programs (1) to (n) are executed on a time-division basis by a single arithmetic-logic unit in the ASIC 30, as shown in FIG. 2. In the programmable controller constructed in this manner, the individual programs are processed on a time-series basis by the single arithmetic-logic unit, so that processing of all the programs takes a long time, as shown in FIG. 2.
(B) Hardware comprising a single MPU 10, a single memory 20, and a single ASIC 30. As shown in FIG. 3, the ASIC 30 includes n number of arithmetic-logic units (1) to (n) and a single arbitration circuit 38 and can execute n number of programs (1) to (n) in parallel. As shown in FIG. 4, the time required for the processing of the programs (1) to (n) is an execution time t for the program (program (1) in the example shown in FIG. 4) that requires the longest processing time.
According to the technique (A), as shown in FIG. 2, there is a problem of the long total processing time.
According to the technique (B), as shown in FIG. 3, on the other hand, a plurality of sequence programs are executed by the arithmetic-logic units in the ASIC 30 and the single MPU 10. Therefore, if the ratio of the instructions executed by the MPU to the instructions that constitute each program is high, the possibility of a plurality of programs simultaneously requesting the MPU to execute the instructions increases. Consequently, a problem occurs that the programs are stopped to wait for the execution of the MPU instructions.
FIG. 5 is a diagram illustrating a problem of the prior art techniques and shows how the programs (1) to (3) are processed in parallel by the programmable controller of FIG. 5. Reference numeral 100 denotes the execution instruction time of each MPU, and reference numeral 112 denotes that of each ASIC. Reference numerals 114 and 116 denote program stops.
Since the MPU 10 is singly used, its processing of the program (2) is started on completion of its processing of the program (1). Further, the MPU 10 starts processing of the program (3) on completion of the processing of the program (2). Thus, the singleness of the MPU 10 causes a problem that the MPU execution instructions of a plurality of programs cannot be simultaneously processed so that the programs are stopped.